Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer in Mission Mode

ABSTRACT

Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1&#39;s and 0&#39;s) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.

BACKGROUND

In many of today's integrated circuits (IC's), serializer/deserializer(SerDes) circuits are implemented to enable the IC's to exchangeinformation with each other and with other components at very high datarates. The SerDes circuits generally include a transmitter and areceiver. Typically, information is sent from a transmitter on one IC toa receiver on another IC through a series of analog pulses.Specifically, to send a digital bit of information, a transmitterdetermines whether the bit that it wants to send is a digital 1 or adigital 0. If the bit is a digital 1, the transmitter generates ananalog signal (which may be made up of a single signal or a pair ofdifferential signals) having a positive voltage. If the bit is a digital0, the transmitter generates an analog signal having a negative voltage.After generating the analog signal, the transmitter sends the analogsignal as a pulse having a certain duration to the receiver along acommunications link. Upon receiving the analog signal, the receiverdetermines whether the analog signal has a positive voltage or anegative voltage. If the voltage is positive, the receiver determinesthat the analog signal represents a digital 1. If the voltage isnegative, the receiver determines that the analog signal represents adigital 0. In this manner, the transmitter is able to provide digitalinformation to the receiver using analog signals.

Ideally, the receiver receives analog pulses that closely resemble theanalog pulses that were sent by the transmitter. Unfortunately, due to apulse response effect that is experienced at high data rates, this idealcannot be achieved. In fact, the analog signal that is received by thereceiver often differs from the pulse that was sent by the transmitterby such a degree that it is often difficult for the receiver todetermine whether the received analog signal represents a digital 1 or adigital 0.

To elaborate upon the concept of a pulse response, reference will bemade to the sample pulse response shown in FIG. 1. FIG. 1 shows anexample of what may be received by a receiver in response to a singlepositive-voltage pulse (representing a digital 1) sent by thetransmitter. In the example shown in FIG. 1, the pulse is sent by thetransmitter in time interval x−4 and received by the receiver four timeintervals later beginning with time interval x. Notice that even thoughthe transmitter sent a pulse lasting only a single time interval, thereceiver does not receive that pulse in just a single time interval.Instead, the receiver receives an analog signal that lasts for severaltime intervals. During time interval x, the received signal has amagnitude of h0. During the next time interval (interval x+1), thereceived signal still has a magnitude of h1. During the next severaltime intervals, the received signal still has magnitudes of h2, h3, h4,and so on. Thus, even though the transmitter sent a pulse lasting onlyone time interval, the receiver receives a signal that lasts for manytime intervals.

Because of this pulse response effect, a pulse sent in one time intervalaffects pulses sent in future time intervals. To illustrate, supposethat the transmitter sends another positive-voltage pulse in timeinterval x−3, and that this pulse is received by the receiver beginningin time interval x+1. During time interval x+1, the receiver would sensethe h0 voltage of the pulse sent in time interval x−3. The receiverwould also sense the h1 voltage of the pulse previously sent in timeinterval x−4. Suppose further that the transmitter sends anotherpositive-voltage pulse in time interval x−2, and that this pulse isreceived by the receiver beginning in time interval x+2. During timeinterval x+2, the receiver would sense the h0 voltage of the pulse sentin time interval x−2. The receiver would also sense the h1 voltage ofthe pulse previously sent in time interval x−3. In addition, thereceiver would sense the h2 voltage of the pulse previously sent in timeinterval x−4. Thus, the voltage sensed by the receiver at time intervalx+2 is an accumulation of the effects of the pulses sent at timeintervals x−4, x−3, and x−2 (and even pulses sent at time intervalsbefore x−4). As this example shows, when the receiver senses a voltageduring a time interval, it does not sense the effect of just one pulsebut the accumulation of the effects of multiple pulses. This distortionmay generally be referred to as “intersymbol interference” (ISI). SevereISI problems may prevent receivers from distinguishing symbols andconsequently disrupts the integrity of received signals in acommunications link.

FIG. 1 shows the pulse response for a single positive-voltage pulse. Thepulse response for a single negative-voltage pulse (representing adigital 0) is shown in FIG. 2. Notice that the pulse response of FIG. 2is similar to the pulse response of FIG. 1 except that the voltages arenegative instead of positive. Thus, as shown by FIGS. 1 and 2, theeffect that a pulse has on future pulses will depend on whether thatpulse is a positive-voltage pulse (representing a digital 1) or anegative-voltage pulse (representing a digital 0). If a pulse is apositive-voltage pulse, it will add to the voltages of future pulses.Conversely, if the pulse is a negative-voltage pulse, it will subtractfrom the voltages of future pulses.

As can be seen from the above discussion, a pulse response cansignificantly affect the signals that are received by a receiver. Thus,it is highly desirable in many implementations to ascertain the pulseresponse effect that is experienced by a receiver. Armed with knowledgeof the pulse response, it may be possible to compensate for its effects.It may also be possible to use the pulse response information to adjustthe parameters of the transmitter and/or receiver and perhaps even othercomponents to improve the overall performance of thetransmission/reception process. These and other uses of the pulseresponse information are possible. A point to note is that a pulseresponse is a characterization of the link performance of thecommunications link to which a receiver is coupled. Because eachreceiver is coupled to a different communications link, each receivermay and most likely will experience a different pulse response effect.Thus, a pulse response is determined on a per receiver/communicationslink basis.

A pulse response for a receiver/communications link may be determined bysending a set of predetermined analog pulses (representing apredetermined bit pattern) from a transmitter to a receiver along acommunications link, and capturing a waveform of the signals actuallyreceived by the receiver. Once the waveform is captured, it can beprocessed and compared with an ideal waveform to derive a pulse responsefor the receiver/communications link. The difficult part of thisprocess, however, is capturing the waveform in a practical and feasiblemanner.

One possible approach to capturing the waveform is to implementsufficient sampling and storage components on each receiver to enablethe receiver to capture an oversampled waveform for the signals receivedby the receiver. To illustrate how this may be done, suppose that apredetermined 128 bit pattern is sent by a transmitter to a receiverover 128 time intervals. Suppose further that it is desirable for thereceiver to oversample the signals received by the receiver 48 times(i.e. take 48 samples of the incoming signals per time interval). Tocapture such a waveform, the receiver would need a sampling clock signalthat is 48 times faster than the incoming data clock. During each timeinterval, the receiver would sample the analog signal received duringthat time interval 48 times. For each sample, the receiver would sensean analog signal and convert it into a corresponding x-bit (e.g. 4-bit)digital value. Each x-bit digital value would be stored in a register.At the end of the 128 time intervals, the receiver will have capturedall of the sample values needed to form an oversampled waveform for theincoming signals.

A problem with this approach, however, is that it is quite resourceintensive. In order to capture the entire oversampled waveform, thereceiver would need 48×128 or 6,144 x-bit registers just to store all ofthe digital sample values. In addition, the receiver would need to havecomponents for implementing the sampling and storage functions. Thesecomponents and storage consume a significant amount of chip space. In alarge scale IC (e.g. a microprocessor), which can comprise a very largenumber of receivers, chip space is precious, and in mostimplementations, it is not practical for each receiver to consume alarge amount of chip space. Because of these and other practicalconsiderations, this approach to capturing an oversampled waveformcannot be feasibly implemented in most applications.

One technique for reducing the effect of ISI is to use an adaptiveequalizer such as a decision feedback equalizer (DFE). A DFE may beoperative to compensate for ISI by utilizing digital filteringtechniques. For example, when a pulse response for a communication linkis known, a DFE may include a plurality of taps (e.g., 2 taps, 5 taps,or the like) that are used to cancel the effects (e.g., reduce theeffects from h1, h2, h3, etc.) of previously sent bits on a present bit.The taps or coefficients for a DFE may be generated using any number ofadaptation processes, and may be implemented in any suitable manner.

The importance of accurate data reception motivates communication linkdesigners to design systems that are able to tolerate ISI and othertypes of noise. One quality characteristic that may be used is referredto as voltage margin or simply “margin.” Voltage margin characterizesthe range of voltage and timing values for which a given receiver willproperly determine input signals. That is, the degree to which thevoltage and time can vary without introducing error is termed the“margin” for the communications link.

SUMMARY

Various embodiments herein include one or more of systems, methods,software, and/or data structures to determine voltage margin for ahigh-speed serial data link. Advantageously, the margin determinationmay be made during normal operation of the data link (“mission mode”)such that the performance of the data link is not affected by thevoltage margin measurements. That is, the margin measurements may beperformed “on line” rather than “off line.” To facilitate the voltagemargin measurement, a plurality of digital samples from an analog todigital converter (ADC) may be evaluated to determine the most probablebit values (i.e., digital 1's and 0's) that are represented by thedigital samples. Then, a method may be used to remove or compensate forISI effects from one or more of the digital samples, thereby providingan accurate representation of the voltage margin present in a data link.Subsequently, the voltage margin may be periodically monitored over timeto detect degradation of the data link.

According to a first aspect, a computer-implemented method for measuringvoltage margin in a serial communications link is provided. The methodmay include receiving a plurality of ordered digital values from ananalog to digital converter (ADC) of a receiver, each digital valuecorresponding to a voltage level sampled by the ADC at a time intervalthat corresponds to a symbol sent by a transmitter. Further, the methodmay include determining bit values for each of the digital values, anddetermining intersymbol interference (ISI) information for at least oneof the determined bit values. Once the bit values and ISI informationhas been determined, the method includes calculating voltage margin forthe at least one of the bit values using the digital value from the ADCcorresponding to the bit value and subtracting the determined ISI forthe bit value.

According to a second aspect, a computer system is provided thatincludes a processor and a data storage coupled to the processor. Thedata storage may store a voltage margin monitoring module that isoperative to be executed by the processor to receive a plurality ofordered digital values from an analog to digital converter (ADC) of areceiver, each digital value corresponding to a voltage level sampled bythe ADC at a time interval that corresponds to a symbol sent by atransmitter. The voltage margin monitoring module may further beoperative to be executed by the processor to determine bit values foreach of the digital values by comparing the digital values to areference value, and to determine intersymbol interference (ISI)information for at least one of the determined bit values. Further, thevoltage margin monitoring module may be operative to be executed by theprocessor to calculate voltage margin for the at least one of the bitvalues using the digital value from the ADC corresponding to the bitvalue and subtracting the determined ISI for the bit value.

According to a third aspect, a computer readable medium is provided. Thecomputer readable medium may include instructions, which when processedby a computer, cause the computer to receive a plurality of ordereddigital values from an analog to digital converter (ADC) of a receiver,each digital value corresponding to a voltage level sampled by the ADCat a time interval that corresponds to a symbol sent by a transmitter.The instructions may also be operative to cause a computer to determinebit values for each of the digital values, and determine intersymbolinterference (ISI) information for at least one of the determined bitvalues. In addition, the instructions may also be operative to cause acomputer to calculate voltage margin for the at least one of the bitvalues using the digital value from the ADC corresponding to the bitvalue and subtracting the determined ISI for the bit value.

In addition to the exemplary aspects and embodiments described above,further aspects and embodiments will become apparent by reference to thedrawings and by study of the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a sample pulse response for a positive-voltage pulse.

FIG. 2 shows a sample pulse response for a negative-voltage pulse.

FIG. 3 shows a sample eye diagram representing input signals to anexemplary receiver.

FIG. 4 shows a block diagram of a system in which one embodiment may beimplemented.

FIG. 5 shows a block diagram of an exemplary receiver.

FIG. 6 shows a block diagram of an exemplary output determinationmodule.

FIG. 7 shows a flow diagram of a method for calculating voltage marginfor a receiver.

FIG. 8 shows another flow diagram of a method for calculating voltagemargin for a receiver.

FIG. 9 illustrates a table of bit values and is provided to demonstratean example implementation of the voltage margin calculation method shownin FIG. 8.

DETAILED DESCRIPTION

Various embodiments herein include one or more of systems, methods,software, and/or data structures to determine voltage margin for ahigh-speed serial data link. Advantageously, the margin determinationmay be made during normal operation of the data link (“mission mode”)such that the performance of the data link is not affected by thevoltage margin measurements. That is, the margin measurements may beperformed “on line” rather than “off line.” To facilitate the voltagemargin measurement, a plurality of digital samples from an analog todigital converter (ADC) may be evaluated to determine the most probablebit values (i.e., digital 1's and 0's) that are represented by thedigital samples. Then, a method may be used to remove or compensate forISI effects from one or more of the digital samples, thereby providingan accurate representation of the voltage margin present in a data link.Subsequently, the voltage margin may be periodically monitored over timeto detect degradation of the data link.

FIG. 3 illustrates a simplified eye diagram 300 for a serial data linkthat may be provided to a receiver. The eye diagram 300 is graphed intwo dimensions, voltage and time. The area of the eye 305 represents arange of reference voltages and timing parameters with which datasymbols (i.e., analog pulses representing digital 1's and 0's) may becaptured by a receiver without introducing an error. As can beappreciated, the larger the eye 305, the more margin present in thesystem. Often, system designers desire to have the ability to measurethe margin of a data link so that performance may be measured, problemsmay be detected, and the like. It will be appreciated that thesimplified eye diagr

With reference to FIG. 4, there is shown a block diagram of a system 400in which one embodiment may be implemented. As shown, system 400includes an integrated circuit (IC) 402, an interconnect 406, and avoltage margin monitoring module (VMMM) 410. For the sake of simplicity,only one IC 402 is shown; however, it is noted that the VMMM 410 may beused to service any number of IC's.

As shown in FIG. 4, the IC 402 comprises a plurality of receivers404(1)-404(n). Each receiver 404 is coupled to a correspondingcommunications link for receiving incoming signals sent by acorresponding transmitter (not shown). Each receiver 404 is also coupledto the interconnect 406 to enable the receiver 404 to interact with theVMMM 410. For purposes of the present invention, the interconnect 406may be any type of interconnect (e.g. switches,multiplexers/demultiplexers, crossbar interconnect, wires, etc.) that iscapable of selectively coupling each of the receivers 404 to the VMMM410. When coupled to a receiver 404, the VMMM 410 interacts with thatreceiver to determine and/or monitor the voltage margin for thatreceiver. The voltage margin may then be used to detect degradation incommunication links coupled to the receiver. For example, the voltagemargin may be analyzed over time using statistical processing to detectpotential problems with the receiver and/or communication link.

In one embodiment, the VMMM 410 is an off-chip component. That is, theVMMM 410 is not implemented on the same chip as the IC 402. By movingthe voltage margin measurement capability off-chip, the resourcesrequired to be implemented on the receivers 404 may be minimized. Thisin turn enables the chip space consumed by each receiver 404 to beminimized. Despite the decreased chip space, each receiver 404 may stillbe able to interact with the VMMM 410. Thus, with this arrangement, itis possible to achieve a relatively small consumption of chip space bythe receivers and measurement of voltage margin for the receivers.

In one embodiment, the VMMM 410 includes a processor 412 (or a pluralityof processors) and a storage 414. The processor 412 may be a serviceprocessor that is already present in many large scale systems. If theprocessor 412 is a service processor, then the voltage margindetermination may be achieved without adding any hardware to the system.The processor 412 may execute a set of voltage margin monitoring code416 stored in the storage 414. Under control of the voltage marginmonitoring code 416, the processor 412 may perform the voltage marginmonitoring operations that will be described in later sections. Inaddition to being used to store the voltage margin monitoring code 416,the storage 414 may also be used to store sample values 418 (e.g., ADCsample values) that are received from the receivers 404. Further, thestorage 414 may be operative to store tap group values 420 for anunrolled decision feedback equalizer (DFE) that may be used in thevoltage margin monitoring, as is described further below.

In the embodiment described above, the functionality of the VMMM 410 maybe realized using software (i.e. by having processor 412 execute code416). As an alternative, the functionality of the VMMM 410 may also berealized in hardware, for example, by way of an ASIC or a set ofhardwired logic components. This and other alternative implementationsof the VMMM 410 are within the scope of the present embodiments.

With reference to FIG. 5, there is shown a more detailed block diagramfor a receiver 404 in accordance with one or more embodiments. Any orall of the receivers 404(1)-404(n) in IC 402 shown in FIG. 4 may takethe form of the receiver 404 shown in FIG. 5. As shown, the receiver 404may comprise an analog-to-digital converter (ADC) 502, an outputdetermination circuit 504, a clock circuit 506 (or sampling controlcircuit), a set of sample registers 508, and storage that holds tapgroup values 510 from the output determination circuit 508.

The ADC 502 may be coupled to a communications link to receive incominganalog signals. In response to a sampling clock signal from the clockcircuit 506, the ADC 502 may sample an incoming analog signal at aparticular sampling point, and convert that analog signal into arepresentative x-bit digital value (where x may be any integer greaterthan one, e.g. 4, 8, or the like). The digital value (i.e. the samplevalue) may then be passed to the output determination circuit 504, whichprocesses the digital value to determine whether the received analogsignal represented by the digital value was a digital 1 or a digital 0.In making this determination, the output determination circuit 504 mayimplement some compensation techniques to compensate for the effects ofpreviously sent signals (e.g., post-cursors h1, h2, h3, and the like).For example, the output determination circuit 504 may include a feedforward equalizer (FFE) and/or a decision feedback equalizer (DFE).After this determination is made, the output determination circuit 504may output an appropriate digital bit (digital 1 or 0), which isprovided to an output consumer. In this manner, the receiver 404 is ableto receive an analog signal (or pulse), and turn it into arepresentative digital output bit.

As noted above, the clock circuit 506 provides a sampling clock signalto the ADC 502. It is this sampling clock signal that determines at whatpoint within a time interval the ADC 502 samples an incoming analogsignal. The sampling clock signal may cause the ADC 502 to sample ananalog signal at the beginning of the time interval, at the end of thetime interval, or at some point in between. In one embodiment, thesampling point may be adjusted based upon a jog control signal. This jogcontrol signal may cause the sampling point to be jogged or moved by acertain amount to a different sampling point.

With reference to FIG. 6, there is shown a more detailed block diagramfor an output determination circuit 504 in accordance with one or moreembodiments. As an example, the output determination circuit 504 may bepart of the receiver 404 shown in FIGS. 4 and 5. The outputdetermination circuit 504 may include an optional feed forward equalizer(FFE) 606 that receives a symbol stream from an ADC 502. The FFE 606 maybe operative to minimize pre-cursor ISI (i.e., ISI due to previouslysent symbols). Additionally, the output determination circuit 504 mayinclude a decision feedback equalizer (DFE) that includes a shiftregister 612, a multiplexer 608, and a set of N tap group values C0-CN(or coefficients) stored in a register 614 coupled to the multiplexer608. In operation, the shift register 612 receives a decision symbolstream (i.e., digital 1's and 0's) from a slicer 602 and performsdecision feedback equalization to generate a DFE output. In this regard,an appropriate tap group value C is selected dependent upon thedecisions made by the slicer 602 for one or more previous symbols. Forexample, if the DFE utilizes 5-taps (thereby compensating forpost-cursors h1-h5), particular tap values may be selected dependentupon the previous five symbols determined by the slicer 602. The FFE andDFE outputs may be added by an adder 604 to generate an equalizer outputthat is fed to the slicer 602. The decision symbol stream is generatedby the slicer 602 slicing the equalizer output. The term “slice” refersto the process of selecting an allowable symbol value (i.e., a digital 1or a digital 0) that is nearest to that of the output signal equalizeroutput. Although a specific output determination circuit 504 is shown inFIG. 6, it will be appreciated that other suitable implementations maybe used as well.

FIG. 7 illustrates a flow chart of a process 700 for determining voltagemargin for a receiver in a high speed communications system. As anexample, the process 700 may be realized using software (e.g., by havingthe processor 412 shown in FIG. 4 execute the voltage margin monitoringcode 416). As an alternative, the functionality of the process 700 mayalso be realized in hardware, for example, by way of an ASIC or a set ofhardwired logic components. This and other alternative implementationsof the process 700 are within the scope of the present embodiments.

Generally, the process 700 involves reading a plurality of ADC samplevalues received by a receiver, identifying a highly probable bit pattern(digital 1's and 0's) for those sample values, applying ISI compensationbased on the highly probable bit pattern, and determining a voltagemargin. More specifically, the process 700 includes reading ADC samplesfrom an ADC of a receiver (step 702). For example, the ADC samples maybe read from the sample registers 508 shown in FIG. 5. Each of the ADCsamples may be an n-bit digital number that corresponds to a voltagelevel received at a receiver. For example, each ADC sample may be a4-bit digital value that represents a voltage level between −6.5 LSB and+6.5 LSB. Of course, other suitable values and ranges may be used asdesired. In general, the number of ADC samples read may be selecteddependent upon the number of taps in a DFE, number of taps in an FFE,the number of voltage margin calculations desired for each iteration ofthe process 700, or other considerations.

Next, the process 700 includes reading tap group values (or DFEcompensation values) for a DFE of a receiver (step 704). For example,the tap group values may be read from the storage 414 shown in FIG. 4.Each tap group value may correspond to a particular DFE compensation tobe applied to an ADC sample value dependent on previously receivedsamples. As described above with reference to FIG. 6, a particular tapgroup value may be applied to an ADC sample to reduce the effects of ISIdue to previous sample values. For example, in the case of a 5-tap DFE,each tap group value may relate to a compensation value for a particular5-bit pattern (e.g., one tap group value for the 5-bit pattern 00000,another tap group value for the 5-bit pattern 10101, and the like).Continuing with the 5-tap DFE example, there may be 2⁵ or 32 possibletap group values corresponding to the possible 5-bit patterns, althoughthere may be repetitive values due to symmetry.

Once the DFE tap group values have been read, the individual tap valuesh for the DFE may be determined (step 706). Since each of the tap groupvalues C correspond to the individual tap weights h for a particular bitpattern, a matrix equation may be solved for the individual tap values husing the previously read tap group values C and the bit patterns forthe individual tap values.

Next, the process 700 may include determining a bit pattern for theplurality of ADC samples using the magnitudes of the ADC samples and theindividual DFE tap values (step 708). For example, this step may includecomparing each ADC sample to one or more threshold values, comparing ADCsamples with each other, applying individual DFE tap values to the ADCsamples, and the like. The result of this step is to provide a highlyprobable bit pattern for the ADC samples read. For example, in the casewhere the plurality of ADC samples includes 5 samples, the output ofthis step may be a bit pattern such as 10010, or the like. It should beappreciated that for some groups of ADC samples, it may not be possibleto determine a bit pattern with a relatively high probability. In thesecases, the process 700 may throw out a set of ADC samples and restartthe process with a fresh set of ADC samples.

Once a highly probable bit pattern has been determined, the voltagemargin for one or more of the bits may be calculated using thedetermined bit pattern, the magnitude of the ADC sample for the bitbeing tested, and the DFE tap group values that were previouslydetermined (step 710). As can be appreciated, in an ideal communicationslink, the magnitude of a symbol read by a receiver would measure thecursor pulse (h0). Therefore, using the voltage margin calculation, asystem may monitor the voltage margin over a period of time to determineits deviation from h0 and/or whether the voltage margin is changing overtime. As an example, a changing voltage margin may be indicative ofmechanical or electrical problems with the communications link. As canbe appreciated, users of a system may wish to further inspect, repair,or replace systems that have degraded voltage margin such thatreductions in performance may be reduced.

FIGS. 8 and 9 illustrate a process 800 (FIG. 8) and a table (FIG. 9) forperforming a voltage margin calculation in a receiver in a high speedcommunications system. In general, the process 800 is a specificembodiment of the process 700 shown in FIG. 7. Similar to the process700, the process 800 may be realized using software (e.g., by having theprocessor 412 shown in FIG. 4 execute the voltage margin monitoring code416). As an alternative, the functionality of the process 800 may alsobe realized in hardware, for example, by way of an ASIC or a set ofhardwired logic components. This and other alternative implementationsof the process 800 are within the scope of the present embodiments.

The process 800 begins by reading eight consecutive ADC samples from anADC of a receiver (step 802). In the table shown in FIG. 9, these ADCsamples correspond to eight bits b1-b8. The ADC samples are 4-bit valuesthat represent voltage levels that range from −6.5 LSB to +6.5 LSB. Ascan be seen, the ADC sample values for bits b1-b8 are −6.5, −6.5, −6.5,+0.5, −4.5, +2.0, −5.0, and +6.5, respectively.

In this example, the receiver system includes a 5-tap DFE that isoperative to compensate for ISI due to the five previously sent symbols.That is, for bit b6, the DFE will compensate for ISI due to bits b1-b5.Similarly, for bit b7, the DFE will compensate for ISI due to bitsb2-b6. Similar to the DFE shown in FIG. 6, the DFE in this exampleincludes a plurality of tap group values, each tap group valuecorresponding to a compensation value for a particular 5-bit pattern.For example, there may be one tap group value C for the 5-bitcombination +1, +1, −1, +1, and −1, and another tap group value for the5-bit combination +1, −1, −1, +1, and +1. As can be appreciated, eachtap group value for a particular bit pattern comprises a weighted sum ofindividual tap values h1-h5 for each bit in a particular bitcombination.

The process 800 includes reading the DFE tap group values from the 5-tapunrolled DFE (step 804) and determining individual tap values h1-h5using the DFE tap group values. As noted above, step 804 may beperformed by solving a set of linear equations which equate the set ofDFE tap group values to a linear combination of tap values h1-h5.

The process 800 also includes determining the probability for the fourpossible 2-bit combinations (i.e., 00, 11, 01, and 10) for pairs of thevarious bit positions b1-b8 to begin to construct a highly probably8-bit pattern (step 808). In this example, the nominal value for adigital 1 is +4.5 LSB, and the nominal value for a digital 0 (alsorepresented by a −1) is −4.5 LSB. Of course, other values may be used inother configurations. In this step, each of the ADC sample values iscompared with +4.5 and −4.5. If an ADC sample value is greater than+4.5, that sample is assigned the bit value of +1. Conversely, if an ADCsample value is less than −4.5, that sample is assigned the bit value of−1 (or a digital 0). It is noted that these assignments are reasonablebecause the ISI required to affect a symbol so greatly that a bit valueof −1 is measured at greater than +4.5 (or a bit value of +1 is measuredat less than −4.5) is highly improbable. As a result of this comparison,bits b1, b2, and b3 are assigned to a value of −1, and bit b8 isassigned to a value of +1. In addition to comparing the individualmagnitudes of the ADC sample values, the difference between adjacent ADCsamples is also compared. That is, if the difference between an ADCsample and a previous ADC sample is greater than +4.5, then the 2-bitpattern −1, +1 is assigned to the bits being compared. Similarly, if thedifference between a sample and a previous sample is less than −4.5, the2-bit pattern +1, −1 is assigned to the bits being compared. The resultsof this step are shown in the table of FIG. 9. As can be seen, in thisexample, all eight bit positions b1-b8 have been assigned a value. Itshould be appreciated that for some groups of ADC sample values,probable 2-bit patterns may not be determined for every bit in thegroup. In these cases, the process may throw out the eight ADC samplesand restart with a new set of samples.

Once the probable 2-bit patterns have been constructed, highly probable3-bit patterns may be determined (step 810). To construct each 3-bitpattern, an ADC sample is compared to −4.5 and +4.5 as in step 808,except that the ISI information for the previous two bits (i.e., h1 andh2) is utilized in addition to the ADC sample value. For example, forbit b5, the ADC sample value (−4.5) and the ISI information for bits b3and b4 (i.e., h1 for bit b4 and h2 for bit b3) are compared to thereference values −4.5 and +4.5. In this regard, the 2-bit patternsdetermined in step 808 and the individual tap values h1 and h2 are usedto construct multiple, highly probable 3-bit patterns. As with the 2-bitpatterns, for some groups of ADC samples, it may not be possible usingthe process 800 to construct 3-bit patterns that cover all eight bitsb1-b8. In these cases, the process 800 may throw out the eight ADCsamples and restart with a new set of samples.

Next, the process 800 may construct highly probable 8-bit pattern usingthe sets of 3-bit patterns by stitching the 3-bit patterns together(step 812). The result of this step is shown in the table of FIG. 9.Once the bit values for all eight bits b1-b8 have been determined, thevoltage margin for bits b6, b7, and b8 may be calculated using the ADCsample value for each bit and the DFE tap group values (step 814). Theresults of this step are shown in the table of FIG. 9. As can be seen,the voltage margin Vm for bit b6 is determined by solving for themagnitude of the ADC sample for bit b6 (i.e., +2) minus the ISIinformation for bits b1-b5 (i.e., the DFE tap group value for the bitpattern −1, −1, −1, +1, and −1, which corresponds to the determinationsmade for bits b1-b5). Similarly, the voltage margin Vm for bits b7 andb8 may be calculated using the ISI information for bits b2-b6 and bitsb3-b7, respectively. It should be appreciated that in systems thatinclude a feed forward equalizer (FFE) in addition to a DFE, the FFEcompensation may need to be included in the voltage margin calculationas well.

As noted above, an ideal voltage margin value in this example would be4.5, which corresponds to the magnitude of an ideal voltage pulse (h0).However, in practice the actual voltage margin may differ from thisideal due to various approximations and system imperfections. Oncedetermined, the voltage margin may then be periodically calculated andmonitored to detect potential problems with the receiver and/orcommunications link. The monitoring may include any type of monitoring,including statistical analysis of the voltage margin over time.Additionally, the monitoring may provide alerts to system operators toprovide an indication of reduced performance or failure of the system.Those skilled in the art will readily recognize other ways in which thedetermined voltage margins may be used by a system.

While this specification contains many specifics, these should not beconstrued as limitations on the scope of the disclosure or of what maybe claimed, but rather as descriptions of features specific toparticular embodiments of the disclosure. Certain features that aredescribed in this specification in the context of separate embodimentscan also be implemented in combination in a single embodiment.Conversely, various features that are described in the context of asingle embodiment can also be implemented in multiple embodimentsseparately or in any suitable subcombination. Moreover, althoughfeatures may be described above as acting in certain combinations andeven initially claimed as such, one or more features from a claimedcombination can in some cases be excised from the combination, and theclaimed combination may be directed to a subcombination or variation ofa subcombination.

Similarly, while operations are depicted in the drawings in a particularorder, this should not be understood as requiring that such operationsbe performed in the particular order shown or in sequential order, orthat all illustrated operations be performed, to achieve desirableresults. In certain circumstances, multitasking and/or parallelprocessing may be advantageous. Moreover, the separation of varioussystem components in the embodiments described above should not beunderstood as requiring such separation in all embodiments, and itshould be understood that the described program components and systemscan generally be integrated together in a single software and/orhardware product or packaged into multiple software and/or hardwareproducts.

1. A computer-implemented method for measuring voltage margin in aserial communications link, the method comprising: receiving a pluralityof ordered digital values from an analog to digital converter (ADC) of areceiver, each digital value corresponding to a voltage level sampled bythe ADC at a time interval that corresponds to a symbol sent by atransmitter; determining bit values for each of the digital values;determining intersymbol interference (ISI) information for at least oneof the determined bit values; and calculating voltage margin for the atleast one of the bit values using the digital value from the ADCcorresponding to the bit value and subtracting the determined ISI forthe bit value.
 2. The method of claim 1, wherein the determining bitvalues step comprises comparing the digital values to a reference value.3. The method of claim 1, wherein the step of determining bit valuescomprises comparing at least one of the ordered digital values with anadjacent digital value.
 4. The method of claim 1, wherein the ISIinformation is obtained from at least one of a feed forward equalizerand a decision feedback equalizer (DFE).
 5. The method of claim 1,wherein the determining ISI information comprises retrieving a pluralityof tap group values for an unrolled decision feedback equalizer (DFE)and determining individual tap values based on the tap group values. 6.The method of claim 1, wherein the determining bit values step furthercomprises: comparing the digital values to a reference value; comparingat least one of the ordered digital values with an adjacent digitalvalue; and applying ISI compensation to the digital values; comparingthe ISI-compensated digital values to a reference value.
 7. The methodof claim 1, wherein the calculating voltage margin step includesapplying feed forward equalization (FFE) compensation.
 8. The method ofclaim 1, further comprising: monitoring the voltage margin for thecommunication for a period of time.
 9. The method of claim 8, whereinthe monitoring step includes analyzing the voltage margin for thecommunication link using statistical analysis.
 10. A computer system,comprising: a processor; and a data storage coupled to the processor,the data storage storing a voltage margin monitoring module that isoperative to be executed by the processor to: receive a plurality ofordered digital values from an analog to digital converter (ADC) of areceiver, each digital value corresponding to a voltage level sampled bythe ADC at a time interval that corresponds to a symbol sent by atransmitter; determine bit values for each of the digital values bycomparing the digital values to a reference value; determine intersymbolinterference (ISI) information for at least one of the determined bitvalues; and calculate voltage margin for the at least one of the bitvalues using the digital value from the ADC corresponding to the bitvalue and subtracting the determined ISI for the bit value.
 11. Thecomputer system of claim 10, wherein the voltage margin monitoringmodule is further operative to be executed by the processor to determinebit values by comparing at least one of the ordered digital values withan adjacent digital value.
 12. The computer system of claim 10, whereinthe ISI information is obtained from at least one of a feed forwardequalizer (FFE) and a decision feedback equalizer (DFE).
 13. Thecomputer system of claim 10, wherein the voltage margin monitoringmodule is further operative to be executed by the processor to determineISI information by retrieving a plurality of tap group values for anunrolled decision feedback equalizer (DFE) and determining individualtap values based on the tap group values.
 14. The computer system ofclaim 10, wherein the voltage margin monitoring module is furtheroperative to be executed by the processor to determine bit values by:comparing the digital values to a reference value; comparing at leastone of the ordered digital values with an adjacent digital value;applying ISI compensation to the digital values; and comparing theISI-compensated digital values to a reference value.
 15. The computersystem of claim 10, wherein the calculating voltage margin step includesapplying feed forward equalization (FFE) compensation.
 16. The computersystem of claim 10, further comprising: monitoring the voltage marginfor the communication for a period of time.
 17. The computer system ofclaim 16, wherein the monitoring step includes analyzing the voltagemargin for the communication link using statistical analysis.
 18. Acomputer readable medium, with instructions which when processed by acomputer cause the computer to: receive a plurality of ordered digitalvalues from an analog to digital converter (ADC) of a receiver, eachdigital value corresponding to a voltage level sampled by the ADC at atime interval that corresponds to a symbol sent by a transmitter;determine bit values for each of the digital values; determineintersymbol interference (ISI) information for at least one of thedetermined bit values by utilizing information received from a decisionfeedback equalizer (DFE); and calculate voltage margin for the at leastone of the bit values using the digital value from the ADC correspondingto the bit value and subtracting the determined ISI for the bit value.19. The computer readable medium of claim 18, wherein the instructionsare further operative to, when processed by a computer, cause thecomputer to: determine bit values by comparing at least one of theordered digital values with an adjacent digital value.
 20. The computerreadable medium of claim 18, wherein the instructions are furtheroperative to, when processed by a computer, cause the computer to:retrieve the ISI information from at least one of a feed forwardequalizer (FFE) and a decision feedback equalizer (DFE).